1. Field of the Invention
The present invention generally relates to a phase modulator and, more particularly, a phase modulator capable of being used as, e.g., a jitter modulator or generator for the jitter tolerance testing of a digital communication system to generate a phase-modulated signal obtained by shifting the phase of a signal to be modulated in accordance with the amplitude and frequency of a modulating signal.
2. Description of the Related Art
In recent years, the importance of digital communication systems have been increasing as an infrastructure for supporting an information-oriented society for a future generation.
The ITU-T (predecessor: CCITT) recommends a new synchronous network interface called an SDH (Synchronous Digital Hierarchy) as a basic network for digital communication systems.
Apparatuses to be incorporated in such an SDH system are being developed and put into practical use by PTTs and communication equipment manufacturers in the world.
One of the important factors in measurements of SDH apparatuses and systems is jitter defined as an instantaneous fluctuation in which the phase of a signal is advanced/delayed with respect to an ideal time position due to crosstalk or reflection of digital lines.
To manage jitter contained in an SDH system, the ITU-T.sup.2) defines that the input jitter tolerance of an apparatus to be measured must exceed a predetermined jitter mask for each bit rate as one of the jitter requirement specifications in the bit rates up to STM-16 (2488.32 Mb/s).
One of the test items in testing performance of each type of communication equipment incorporated in a communication network is a jitter tolerance testing.
In general, signals to be input to a variety of communication equipments are often transmitted through, e.g., long-distance optical fiber cables, microwave lines, and satellite communication channels.
These signals may often be transmitted through a large number of repeaters or measuring instruments.
A phenomenon in which the phases of the signals are offset due to the above causes in the communication lines or channels is called "jitter". The jitter tolerance testing is to measure a maximum degree of phase offset with which each communication equipment can accurately receive a signal.
A signal jitter-modulated with a sinusoidal wave is used in this measurement which is performed together with a code error measurement.
More specifically, at an arbitrary sinusoidal jitter modulation frequency, a jitter amount is gradually increased, and a value obtained immediately before occurrence of an error is defined as an input jitter tolerance.
To measure jitter tolerance characteristics of each communication equipment, a phase-modulated signal having an arbitrary modulation degree and an arbitrary modulation frequency must be generated and applied to a target communication equipment.
An arrangement using a phase-locked loop (PLL) circuit as a Jitter modulator or generator, i.e., a phase modulator for generating this phase-modulated signal, is proposed in, e.g., U.S. Pat. No. 4,810,977.
The phase modulator using this PLL circuit has an arrangement, as shown in FIG. 5.
An input signal a (=sin.omega..sub.S t) of a predetermined carrier angular frequency .omega..sub.S input from an input terminal 1 is frequency-divided into an 1/N signal by a frequency divider 2.
An input signal b (sin.omega..sub.S t/N) whose frequency is 1/N-divided by the frequency divider 2 is input to a phase comparator (PD) 3 connected to the output of the frequency divider 2.
The phase comparator 3 detects a phase difference .DELTA..theta. between the input signal b whose frequency is 1/N-divided by the frequency divider 2 and a frequency-divided signal c output from another frequency divider 9.
The high-frequency component of a phase difference signal d (=.DELTA..theta.) output from the phase comparator 3 is removed by a low-pass filter (LPF) 4, and an output signal from the low-pass filter 4 is input to one input terminal of an adder 5.
An FM signal g represented by equation (1) is input from a frequency-demodulated (FM) signal generator 6 to the other input terminal of the adder 5. EQU g=sin .omega..sub.M t=sin (.omega..sub.0 t-m.sub.f cos pt) (1)
.omega..sub.0 : the reference angular frequency PA1 p: the modulating angular frequency PA1 m.sub.f : the modulation index PA1 first frequency conversion means for mixing an input signal having a predetermined carrier frequency with the FM signal from the FM signal generating means; PA1 first signal extracting means for extracting one of upper and lower sideband signals obtained from the first frequency conversion means as an intermediate frequency signal; PA1 delay means for delaying the intermediate frequency signal from the first signal extracting means by a predetermined time in order to set the modulation degree in the phase modulator; PA1 second frequency conversion means for mixing the intermediate frequency signal delayed by the delay means with the FM signal from the FM signal generating means; and PA1 second signal extracting means for extracting a frequency signal corresponding to the carrier frequency component of upper and lower sideband signals obtained from the second frequency conversion means. PA1 first frequency conversion means for mixing an input signal having a predetermined carrier frequency with the FM signal from the FM signal generating means; PA1 first signal extracting means for extracting one of upper and lower sideband signals obtained from the first frequency conversion means as an intermediate frequency signal; PA1 delay means for delaying the intermediate frequency signal from the first signal extracting means by a predetermined time in order to variably set the modulation degree in the phase modulator; PA1 second frequency conversion means for mixing the intermediate frequency signal delayed by the delay means with the FM signal from the FM signal generating means; and PA1 second signal extracting means for extracting a frequency signal corresponding to the carrier frequency component of upper and lower sideband signals obtained from the second frequency conversion means.
The adder 5 adds the phase difference signal e and the FM signal g and outputs a sum signal h to a voltage-controlled oscillator (VCO) 7 connected to the output of the adder 5. EQU h=e+g=.DELTA..theta.+sin (.omega..sub.0 t-m.sub.f cos pt) (2)
The VCO 7 outputs an output signal i having a frequency changing in proportion to the signal level of the sum signal h.
The output signal i from the VCO 7 is externally output from an output terminal 8 of the phase modulator and applied to the frequency divider 9.
The frequency divider 9 frequency-divides the output signal i from the VCO 7 into a 1/M signal, and this signal is output as a frequency-divided signal c to the phase comparator 3.
The frequency division ratio 1/M of the frequency divider 9 is set to match the frequency of the frequency-divided signal c input to the phase comparator 3 with the frequency of the input signal b.
The frequency division ratios 1/N and 1/M of the frequency dividers 2 and 9 can be manually changed by an operator at an operation unit 10.
A closed loop comprising the phase comparator 3, the LPF 4, the adder 5, the VCO 7, and the frequency divider 9 constitutes a kind of phase-locked loop (PLL) circuit.
In the phase modulator incorporating this PLL circuit, the input signal a input from the input terminal 1 of the phase modulator is frequency-divided into an 1/N signal by the frequency divider 2, and this frequency-divided signal is input to the PLL circuit.
In this PLL circuit, the sum signal h input to the VCO 7 has a waveform on which the phase difference signal e is superposed.
A phase .theta. of the 1/N input signal b changes in accordance with a change in instantaneous value of the FM signal g input through the adder 5.
The final change appears as a change in phase of the output signal i from the VCO 7.
The output signal i appearing at the output terminal 8 is a phase-modulated signal whose phase .theta. changes in accordance with a change in instantaneous value of the FM signal g.
The phase modulation characteristics of this phase-modulated signal are a modulation frequency representing a rate of change in phase in phase modulation and a modulation degree representing a phase change range, e.g., a time width in phase modulation.
In this case, the modulation frequency corresponds to the rate of change in instantaneous value of the FM signal g, i.e., the modulating angular frequency p of the FM signal g. For this reason, to change the modulation frequency, the modulating angular frequency p of the FM signal g is changed.
The modulation degree corresponds to the change width of the instantaneous value of the FM signal g, i.e., the amplitude thereof.
To change the modulation degree, the amplitude of the FM signal g is changed.
When the amplitude of the FM signal g is increased to increase the modulation degree, an output from the adder 5 is undesirably saturated.
The phase comparator 3 generally detects only the phase difference .DELTA..theta. in the phase range of 200.degree. to 300.degree..
The frequency divider 2 is inserted in the input stage of the PLL circuit to reduce the frequency of the input signal b input to the phase comparator 3 in the PLL circuit.
With this arrangement, a larger time width, i.e., a larger modulation degree can be obtained than a case wherein the amplitude of the FM signal g is changed to obtain an identical phase difference .DELTA..theta..
To change the modulation degree of the phase-modulated signal (output signal i), the amplitude of the FM signal g is not changed, but the frequency division ratio 1/N of the frequency divider 2 is generally changed.
The modulation frequency and modulation degree of the phase-modulated signal (output signal i) from the phase modulator shown in FIG. 5 can be changed to arbitrary values.
The phase modulator using the PLL circuit shown in FIG. 5, however, still has the following problem left unsolved in practice.
More specifically, when the frequency division ratio 1/N of the frequency divider 2 is increased to increase the modulation degree in phase modulation, the frequency of the input signal b input to the PLL circuit is reduced.
When the frequency is reduced, the cutoff frequency of the LPF 4 incorporated in the PLL circuit must be decreased accordingly.
As a result, the frequency response characteristics of the entire PLL circuit are degraded to reduce the loop gain.
In this state, even if the modulating angular frequency p of the FM signal g is increased to increase the modulation frequency in phase modulation, this change is absorbed in the PLL circuit and does not appear in the output signal i.
To increase the modulation frequency, the modulating angular frequency p of the FM signal g must be increased, and at the same time, the frequency division ratio 1/N of the frequency divider 2 is set low, thereby increasing the cutoff frequency of the LPF 4.
When the frequency division ratio 1/N of the frequency divider 2 is set low, the modulation degree in phase modulation cannot be set large.
In this manner, in the phase modulator using the PLL circuit, the modulation degree in phase modulation for the output phase-modulated signal is closely related to the modulation frequency. It is very difficult to set the other factor to an arbitrary value while fixing one factor. Therefore, both the factors cannot be simultaneously set at large values.
FIG. 6 is a graph showing the relationship between the set modulation degree and the set modulation frequency in the phase modulator shown in FIG. 5.
As can be apparent from FIG. 6, for example, when the modulation degree is set large, the modulation frequency cannot be set high. To the contrary, when the modulation frequency is set high, the modulation degree becomes small.
As a result, the conventional phase modulator using the FM modulator constituted by the PLL circuit, as shown in FIG. 5, has limitations for generating a phase-modulated signal having an arbitrary modulation degree and frequency which are required to measure the jitter tolerance characteristics of each communication equipment described above.